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Količina | |
---|---|
1+ | € 10,800 |
10+ | € 7,870 |
25+ | € 7,560 |
100+ | € 7,240 |
300+ | € 7,100 |
500+ | € 6,950 |
INFORMACIJE O IZDELKU
Pregled izdelka
The DS1100LZ-50+ is a 3.3V 5-tap economy timing element (delay line) in 8 pin NSOIC package. It is characterized for operation over the range 3V to 3.6V. The DS1100LZ-50+ delay line has five equally spaced taps. It is offered in surface-mount packages to save PCB area. This 5-tap silicon delay line reproduces the input-logic state at the output after a fixed delay of 50ns and it has 10ns delay time per tap. It is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to 10 74LS loads.
- Supply voltage range is 3V to 3.6V
- Operating temperature range from -40°C to 85°C
- Delays are stable and precise
- Low power CMOS and TTL/CMOS compatible
- Vapour phase and IR solderable
Področja uporabe
Clock & Timing
Opozorila
Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.
Opombe
ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party
Tehnični podatki
50ns
5
3.6V
8Pins
85°C
MSL 1 - Unlimited
10ns
3V
NSOIC
-40°C
-
No SVHC (21-Jan-2025)
Tehnični dokumenti (2)
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